Abstract:  describes the use of modern EDA design tools commonly used in nuclear physics experiment instruments - scaler principle and method. The calibration of new devices on the system using FPGA technology to integrate large quantities of the circuit, combined with AT89C51 microcontroller to control and treatment, and increase the data storage function and RS232 interface, to achieve and PC computer communication, for data processing. This paper presents the design details of the new scaler detailed schematic and FPGA design.   Keywords:  GM counter scaler Field Programmable Gate Array (FPGA)  <P style = \30px \use high voltage power supply and scaler, and currently available equipment is commonly used discrete components, has serious aging, high pressure and extremely unstable, is also more difficult to maintain; the other hand, apparent lack of many common features, so students The experimental course difficult to maintain. To this end we propose a new design: the structural design using EDA, give full play to FPGA (Field Programmable Gate Array) technology, integrated features and discard the original number of transistor circuits, the system successfully carried out a large number of processing circuits simplification and intensive, improve equipment reliability and stability, conducive to the circuit testing and maintenance. Improve the program from the calibration device is not only the original sound of the Gong Neng, also added Shuojucunchu, RS232 interface, Deng function, can easily communicate with the PC machine Jie Kou, data processing, image Xianshi He Dayin so.   β  Ray Bell type and is mainly used for detecting  γ  Ray's long cylindrical. One bell-type  β  counter operating voltage 1000 V (V) around cylindrical operating voltage close to 1000 V (volts).  <P style=\C, sent by pre-amplifier scaler count, shown in Figure 1. As the count after the termination of the discharge pipe will form a continuous discharge phenomenon, the Xian right count tube extremely Youhai, Gu Zeng Jia a Faxian count when suddenly, the Ying immediately Jiangdigaoya. Improved scaler will control high-voltage source, its voltage decreases. These improvements. Can be avoided before the experiment appears counter corruption problems.    GM counter through the input of negative pulse shaping circuit for shaping, amplification processing, generate standard TTL signal, measured by the counting circuit count. Time gating circuit control pulse width count, sub-6 file: × 10 -3, × 10 -2, × 10 -1, × 10 0, × 10 1, × 10 2. Time profile of 4 multiplying choices: × 1, × 2,p90x on sale, × 4,MAC Cosmetics Wholesale, × 8. Such conduct is a set of measurement data generated can be used to describe the laws of ray particles.  <P style=\At the same time according to need, select the part of the measurement data (including the count data and the corresponding pressure value) stored in RAM, then the selected data in RAM, sent through the RS232 serial port to the PC, after appropriate processing software drawings, and the corresponding experimental data processing. In order to make the system more integrated, a specific pulse width when the door control, counting measurement circuit, address decoding and data latches, bus drivers and other circuits integrated into a FLEX10K the FPGA. Figure 3 details circuit block diagram for the system.  <P style=\Design  <P style=\FPGA logic to achieve the following main functions: regular pulse gating, counting measure, address latch, decoder, bus drivers and expansion as well as digital display control functions. Top-level structure of the logic function shown in Figure 4. Select Altera FPGA device company FLEX10K10 series EPF10K10LC84-4 chip. The chip has 10,000 equivalent logic gates, with 572 logic cells (LEs), 72 logic array blocks (LABs), 3 个 embedded array block (EAB s), and has 720 on-chip registers can be In the off condition of internal resources to achieve 6144 bit on-chip memory; internal modules using high-speed, latency and predictable fast-track connection; logical unit between the high-speed, high fan-out of the cascade chain and fast carry chain; film There is also tri-state network and the six global clock, four global clear signal, and a wealth of I / O resources; each I / O pins can be selected for the tri-state control or open-collector output can be programmed to control each I / O pins of the speed and I / O register usage.  <P style=\The software is a set of design entry, compilation, simulation and programming as one of the super-integrated environment; to provide an automatic logic synthesis tools, can be multiple logical level description of a comprehensive senior design, optimization, greatly reducing compile time, speed the FPGA design and development process. MAX + PLUS II supports a variety of HDL input options, including VHDL, Verilog HDL and ALTERA the hardware description language AHDL; provide a rich library unit calls for designers, including all 74 series logic devices and a variety of special macros unit (macrofunction), and the giant new parameterized unit (magafunction).   FPGA design has four basic stages: design entry, design build, design verification,p90x on sale, and device programming. First of all, the logic function generated according to the system top-level structure diagram, shown in Figure 4. Then divided into several small modules of a design under. This top-down analysis of the logic function, design build from the ground, each one is to test and verify. When the last top-level module in the wave simulation logic functions satisfy the system timing requirements, the device can be programmed.  <P style=\SRAM cell must be loaded in the device configuration data after power up and configuration is completed, its memory and I / O pins must be the beginning of. After initialization, the device into the user mode, start the system running. For FLEX10K devices, Altera offers four kinds of configurations: EPC1 (or EPC1441) EPPOM configure, passive serial, passive parallel synchronous method, passive parallel asynchronous method. Configure the device, we first use the passive serial method (passive serial). This way is by downloading the cable to the device configuration, suitable for debugging stage. When the system is complete, use EPPOM way to configure the device. This solidified the data in the EPROM on the system configuration when the power of the FPGA chips, EPROM chips which use EPC1441.  <P style=\latch, decoder, bus drivers, expansion module that three major modules. Pulse counting and timing module in which control module is used to achieve a count of the number of input pulse measurement; address latch, decoder, bus drivers and expand this part of the module, the main achievement of the time sharing of data transmission in the bus. The data bus includes pulse counting data and high-voltage power supply module data, and from the MCU data bus D0 ~ D7 digital display with the data. This module addresses decoding part, to provide chip select signal latch unit. Figure 5 shows the FPGA top-level circuit.   Specific design, taking into account the count pulse width of 0.1 ~ 100  μs , the maximum count rate of 2MHz,insanity workout, the median count of 7 bit,MAC Cosmetics Wholesale, so the design of the pulse good number of modules equivalent to a 7-bit of BCD plus counter; the timing control module is equivalent to a 7 in the BCD by counter. Preset by the initial value of the counter by the timer select switch control to control the number of times. CLR signal to \This part of the design by calling the provided MAX + PLUS II AHDL language library functions combined with a graphical input to complete. Address decoding, latched, the bus driver module mainly by D flip-flops and I / O interface design is made. As the data transmission using the bidirectional input / output ports, but the Altera chip pin port can not be used directly, and needs a three-state logic gates, therefore, bus interface part is that two kinds of function prototypes (three-state door and two-way port) for composite design.  <P style=\stringent design verification before continuing on a layer of design. Here the main use of the TIMER MAX PLUS II waveform simulation, to verify the functions of the modules to determine whether to meet the requirements of its timing. If the timing slightly wrong, or even just a small glitch, we must immediately change the input design. Thus, only the high precision design, the system becomes stable work. When the end of each module in sequential logic functions to meet the demand on the design to be completed. Figure 6 for the FPGA in <DIV class=\  More articles related to topics：

  
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