Vivado Design Suite 静态时序分析和 Xilinx 设计约束培训课程

 Vivado Design Suite 静态时序分析和 Xilinx 设计约束培训课程

Vivado Static Timing Analysis and Xilinx Design Constraints

Who Should Attend?

FPGA designers with intermediate knowledge of HDL and FPGA architecture, and some experience with the Xilinx Vivado Design Suite

Course Outline

 1

• Review of Essentials of FPGA Design
• Design Methodology Summary
• FPGA Design Techniques
• Accessing the Design Database
• Lab 1: Vivado IDE Database
• Static Timing Analysis and Clocks
• Lab 2: Vivado Clocks

 2

• Inputs and Outputs
• Lab 3: I/O Constraints
• Timing Exceptions
• Lab 4: Timing Exceptions
• Synthesis Techniques
• Appendix: Design Methodology
• Appendix: HDL Coding Techniques

 3

• FPGA Design Methodology Checklist
• FPGA Design Methodology
• HDL Coding Techniques
• Reset Methodology
• Lab 5: Resets
• Lab 6: SRL and DSP Inference
• Synchronization Circuits and the Clock Interaction Report
• Timing Closure
• FPGA Design Methodology Case Study
• Lab 7: Timing Closure and Design Conversion
• Appendix: Timing Constraints Review
• Appendix: Synchronization Circuits and the Clock Interaction Report
• Appendix: Fanout and Logic Replication
• Appendix: Pipelining lab